Clock and Data Recovery PLL Design Considerations in 0.1 um CMOS

This post links to a paper that discusses clock and data recovery PLL design considerations in 0.1 um CMOS.

Link: https://drive.google.com/file/d/10Y_dyytu8LlwLVu9d9cYscNYQD9ZCR4P/view?usp=sharing

References

This and other papers at https://www.researchgate.net/scientific-contributions/Z-Pfeffer-11999069